![]() ![]() AMD Already Using AI to Design Chips, Moving Into Generative AI It's already there today, and you'll see more coming. Paul Alcorn: So, it's probably safe to say that a hybrid architecture will be coming to client ? They're also going to need different core counts and accelerators. And it's going to be in enterprise data centers as well. As AI moves from not only being in the cloud, where the heavy training and large language model inferencing will continue, but you're going to see AI applications in the edge. But many businesses are indeed adding point AI applications and analytics. Certain workloads move more slowly You might be in that sweet spot of 16 to 32 cores on a server. When you go to the data center, you're also going to see a variation. It's not only how you've optimized for either performance or energy efficiency, but stacked cache for applications that can take advantage of it, and accelerators that you put around it. So where, Paul, we're moving to now is not just variations in core density, but variations in the type of core, and how you configure the cores. And the other example in PCs is the Ryzen 7040 we've actually added AI acceleration right into the APU.īut what you'll also see is more variations of the cores themselves, you'll see high-performance cores mixed with power-efficient cores mixed with acceleration. If you do need tailored, extensive acceleration, you can still bolt on a discrete GPU. And that's because it really creates a very dense and power-efficient offering, and if you don't need a high-performance GPU, you can save energy with that sort of tailored configuration. So, if you look at what we've done in desktop for Ryzen, we've actually added a GPU with our CPU. But what you're going to see is that you might need, in some cases, static CPU core counts, but additional acceleration. You're going to have a set of applications that actually are just fine with today's core count configurations because certain software and applications are not rapidly changing. Because it's really now where one size doesn't fit all we're not even remotely close to that. Mark Papermaster: What you're going to see in PCs, as well as in the data center, is more bifurcation of tailored SKUs and processers coming out. So now, today, do you still see a runway for more cores in data center chips? Additionally, do you see the need for more cores in the client space now that it's at 16 cores? It's been two generations with 16, is that going to be a sweet spot moving forward? ![]() AMD was also at 16 cores for Ryzen for desktop PCs, and now you're still at 16 cores for Ryzen - so two generations of 16-core chips for client. At the time AMD was at a peak of 64 cores, and now you're at 96 for Genoa. You said at the time that you see a runway for more cores, and that you don't see a saturation point in the foreseeable future. Paul Alcorn: I interviewed you back in 2019 at the Supercomputing conference and we talked about increasing CPU core counts. First, here’s our interview with Papermaster before his keynote: We’ll cover that and many of the other highlights of the event over the coming days. Papermaster’s presentation centered on the fact that computing is now being gated by power efficiency as Moore’s Law slows. Imec’s ITF World 2023 conference featured a string of keynotes from powerful luminaries in the semiconductor industry, like AMD’s Mark Papermaster, Intel’s Ann Kelleher, Nvidia’s Jensen Huang, imec’s Luc Van de hove, and ASML’s Christophe Fouquet. He's directed AMD's technology development for over a decade, laying the cornerstones of technology that powered the company’s resurgence against industry stalwart Intel, giving him incredible insight into the company's past, present, and future. Mark Papermaster has served as AMD’s Chief Technical Officer (CTO) and SVP/EVP of Technology and Engineering since 2011. We have the full conversation further below. Papermaster also spoke about AMD’s current use of AI in its semiconductor design, testing, and verification phases, and about the challenges associated with the company’s plans to use generative AI more extensively for chip design in the future. These types of designs use larger cores designed for performance mixed in with smaller efficiency cores, much like Intel’s competing 13th-Gen chips. The highlights of the interview include Papermaster’s new revelation that AMD will bring hybrid architectures to its lineup of consumer processors in the future, a first. I met with AMD CTO Mark Papermaster on the sidelines of ITF World, a conference hosted by semiconductor research firm imec in Antwerp, Belgium, for an interview to discuss some of AMD’s plans for the future.
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